1. Field of the Invention
The present invention is directed to methods and devices for clock distribution networks in integrated circuits. More specifically, but without limitation thereto, the present invention is directed to a resonant clock distribution network for an integrated circuit.
2. Description of the Prior Art
High power consumption in clock distribution networks is a problem in large integrated circuit designs in which the clock power dissipation is dominated by dynamic or switching power, which is proportional to the wiring capacitance and the input capacitance of flip-flops connected to the clock net. As a result, high power dissipation and heating may be generated by clock distribution networks.